The present invention relates to a semiconductor device, and particularly relates to a semiconductor device having a capacitor formed between wirings.
Conventionally, an LSI (Large Scale Integrated-circuit) chip is known as a semiconductor device which has a plurality of wirings (multi level inter-contacts).
In the LSI chip, although an external bypass-capacitor can provide high capacitance, it cannot sufficiently deal with and restrain an IR drop of potential of the internal wiring for the power supply because the LSI chip is becoming enlarged in dimension and, accordingly, an internal wiring for a power supply is becoming lengthened in these recent years. Moreover, it is difficult to form the internal wiring for the power supply with a sufficient width because the semiconductor devices in present days are becoming highly integrated and having a high density.
Considering the above, a proposal has been made about a bypass-capacitor (which will be simply referred to as a capacitor hereinbelow) for restraining the IR drop of a power supply line and for stabilizing potential. The capacitor is provided with a capacity film which serves as a gate insulating film formed on the semiconductor chip, a lower electrode serves as a lower substrate formed under the gate insulating film, and an upper electrode serves as an electrode formed on the gate insulating film.
However, because the capacity film is formed on the substrate by using the gate insulating film in the capacitor (bypass-capacitor), the capacitor requires a plenty of space on the periphery portion of the semiconductor device. With this structure, the dimension of the semiconductor device will be inadvantageously enlarged. Furthermore, if a leak occurs due to the reduction of the thickness of the gate insulating film, the capacitor cannot perform efficiently. In addition, because the capacity film cannot be formed on a desired position of the semiconductor device, the capacity film is compelled to be formed on an empty space, in other words, on the region where it is not most suitable for restraining the IR drop.
In order to restrain the IR drop of the power supply line and to stabilize the potential in a multi layer wirings-structure, proposal has been made about a semiconductor integrated circuit and a semiconductor device, each disclosed in Japanese Unexamined Patent Publications (JP-A) Nos. 64284/1997 (Tokkai Hei 9-64284) and 283611/1993 (Tokkai Hei 5-283611), respectively.
The semiconductor integrated circuit has first and second layer wirings superimposed over each other. The first and the second layer wirings serve as first and second power supply wirings, respectively. Between the first and the second power supply wirings, a capacity layer is formed. Consequently, an internal bypass capacitor is formed in the semiconductor integrated circuit.
On the other hand, the semiconductor device has lower and upper layer wirings formed along a peripheral edge region of one main surface of a semiconductor substrate. The lower and the upper layer wirings serve as set potential and power supply wirings, respectively. Between the lower and the upper layer wirings, an inter-layer dielectric film made by a thin insulating film or a high dielectric film is formed. Consequently, a capacitor is formed in the semiconductor device.
However, in the semiconductor integrated circuit, the inter-layer dielectric film cannot be reduced in thickness because the power supply layer wiring and a signal line layer are formed so as to utilize the same layer in common and therefore the semiconductor integrated circuit cannot secure high capacitance between the first and the second layer wirings. If the thickness of the inter-layer dielectric film as the dielectric film is reduced for the purpose of ensuring a practical high capacitance, a coupling capacity of the signal line existing on the same layer as the power supply wiring will be increased. This, as a result, lowers a transmitting speed of the signal. Furthermore, in accordance with the minimization with respect to the pitch or an interval space between each wirings, the inter-layer dielectric film is required to have low dielectric constant.
In the semiconductor device, it is difficult to form small hole on the inter-layer dielectric film because the inter-layer dielectric film is thick. Accordingly, the inter-layer dielectric film should be bored a large hole in advance to forming the upper electrode. For this purpose, the inter-layer dielectric film requires larger width than that of the power supply wiring. This makes a surface of the semiconductor device rough and difficult to make the surface of the semiconductor device flat.
In view of the above, it is an object of the present invention to provide a semiconductor device having a capacitor which assures sufficient and high capacitance without requiring large area only for forming the capacitor. Furthermore, the semiconductor device can restrain an IR drop of a power supply line and can stabilize potential.
The other objects, features, and advantages of the present invention will become clear as the description proceeds.
A semiconductor device to which this invention is applicable comprises first and second layer wirings formed with a space left therebetween and a capacitor which is formed in the space and which is electrically connected to the first and the second layer wirings. The capacitor comprises a via electrically connected to one of the first and the second layer wirings, an electrode made of a conductive material and electrically connected to one of the first and the second layer wirings through the via, and a dielectric film formed between the electrode and another one of the first and the second layer wirings.
A method of producing a semiconductor device according to the invention is applicable to the semiconductor device comprising first and second layer wirings formed with a space left therebetween and a capacitor formed in the space and electrically connected to the first and the second layer wirings. The method comprises the step of forming the lower layer wiring which serves as a lower electrode of the capacitor. The method further comprises the steps of forming a dielectric film on the lower electrode, forming an upper electrode of the capacitor on the dielectric film, forming a via so as to be electrically connected to the upper electrode, and forming an upper layer wiring so as to be electrically connected to the via.